1. Field of the Invention
The present invention relates to a multi-port memory and a system using the same.
Priority is claimed on Japanese Patent Application No. 2008-073614, filed Mar. 21, 2008, the content of which is incorporated herein by reference.
2. Description of Related Art
For a memory accessed by a plurality of processors, a DRAM (Dynamic Random Access Memory) with a multi-port and multi-bank configuration and a control method thereof are conventionally known.
For example, as one example of conventional RAMs, a multi-port RAM is disclosed in Japanese Unexamined Patent Application, First Publication No. H08-221319 (Patent Document 1). This multi-port RAM includes: a plurality of memory banks, each capable of storing data; and a plurality of input/output ports that allow input and output of data, in which the plurality of input/output ports are coupled to the memory banks via different buses.
Furthermore, as another example of conventional RAMs, an SDRAM is disclosed in Japanese Unexamined Patent Application, First Publication No. 2000-215659 (Patent Document 2). This SDRAM includes: m banks, each including a memory cell region where memory cells are arranged, a row selection circuit for selecting a row in the memory cell region, and a column selection circuit for selecting a column in the memory cell; and n ports. This SDRAM further includes a multi-port circuit capable of accessing optional n banks from the n ports independently and simultaneously, where m≧n.
Furthermore, in conventional RAMs, a multi-port DRAM is disclosed in Japanese Unexamined Patent Application, First Publication No. 2002-197853 (Patent Document 3). This multi-port DRAM includes: a plurality of, for example N, external ports each of which receives a command; N sets of buses, each corresponding to each of the external ports; a plurality of memory blocks connected to the N sets of buses; and an address comparison circuit for comparing addresses accessed by a plurality of commands that are each input from the external N ports. This multi-port DRAM further includes a determination circuit for determining, when the address comparison circuit detects accesses to the same memory block through the address comparison, which command is to be executed and which command is not to be executed among the commands that access the same memory block.
Furthermore, in conventional RAMs, an SDRAM control circuit is disclosed in Japanese Unexamined Patent Application, First Publication No. 2003-263363 (Patent Document 4). This SDRAM control circuit includes: a plurality of ports that are connected to a plurality of independently accessible memories; selectors that allocate ports to be accessed based on an apportion bit, the apportion bit being a predetermined bit in a memory access request address from each of a plurality of masters; arbitration devices that arbitrate memory access requests from the plurality of masters, the memory access requests being allocated by the selectors each connected to each port; and access devices that control access to a memory according to contents of the memory access request of the master determined by the arbitration device connected to each of the ports.
Furthermore, in conventional RAMs, a DRAM-type multi-port memory is disclosed in Japanese Unexamined Patent Application, First Publication No. 2003-272378 (Patent Document 5). This DRAM-type multi-port memory includes: a cell array made of volatile memory cells and including a plurality of banks; a plurality of external ports each capable of accessing independent addresses of the cell array; an arbitration circuit that determines the order of access among the plurality of external ports; and a control circuit that outputs a busy signal to one of the plurality of the external ports if, at the time of an access request from the one port to one of the banks of the cell array, the one bank is executing a core operation.
Furthermore, in conventional RAMs, a multi-port RAM system is disclosed in Japanese Unexamined Patent Application, First Publication No. 2005-346715 (Patent Document 6). This multi-port RAM system includes: a plurality of memory banks, a plurality of buses, and a selection mechanism between the memory banks and the buses. This selection mechanism is connected to every memory bank in the plurality of memory banks and to every bus in the plurality of buses. The selection mechanism selects any memory bank from the plurality of memory banks, and allows the selected bank to be connected to any bus from the plurality of buses.
Furthermore, in conventional RAMs, a multi-port semiconductor memory is disclosed in Japanese Unexamined Patent Application, First Publication No. 2007-172811 (Patent Document 7). This multi-port semiconductor memory includes: a plurality of input/output ports different from one another; a memory array divided into a plurality of memory regions different from one another; and a selection control for variably controlling access routes between the memory regions and the input/output ports so that each of the memory regions is accessed via at least one of the input/output ports.
Furthermore, in conventional RAMs, a multi-port DRAM system is disclosed in Published Japanese Translation No. 2000-501524 of the PCT International Publication (Patent Document 8). This multi-port DRAM system for use in a system has a master bus controller having parallel ports and a DRAM each connected for access to a common bus interface. The multi-port DRAM system includes a multi-port internally-cached DRAM, and has a plurality of independent serial data interfaces each connected between a separate external I/O resource and an internal DRAM memory through corresponding buffers. A switching module is interposed between the serial data interfaces and the buffers. In addition, the internally-cached DRAM is controlled by the master bus controller so that a switching module logic dynamically makes a route between the serial interfaces and the buffers.
Furthermore, in conventional RAMs, a memory system is disclosed in Japanese Unexamined Patent Application, First Publication No. H08-212766 (Patent Document 9). This memory system includes: a plurality of memory blocks made of single-port memory cells; global bit lines with a multi-port configuration; and a switch device for selectively connecting bit lines in the memory blocks to the global bit lines, to thereby constitute a pseudo-multi-port memory with a high area efficiency.
Furthermore, in conventional RAMs, a multi-port DRAM is disclosed in Japanese Unexamined Patent Application, First Publication No. 2001-043674 (Patent Document 10). This multi-port DRAM includes: plural sets of common lines; plural sets of memory block groups, each of the groups being made of a plurality of memory blocks commonly connected to each shared line; a first port that accesses the memory blocks; a second port that accesses the memory blocks; a plurality of first switches that electrically connect or disconnect between the first port and the plural sets of common lines; a plurality of second switches that electrically connect or disconnect between the second port and the plural sets of common lines; and a switch control circuit that controls the first switches and the second switches, to thereby make it possible to evade increase in chip area.
However, the aforementioned DRAMs with a multi-port and multi-bank configuration disclosed in Patent Documents 1 to 10 have a problem in that it is not possible to perform a simultaneous write operation from one input/output port to a plurality of banks, and conversely, to perform a simultaneous read operation from one bank to a plurality of input/output ports.
On the other hand, as a configuration that solves the aforementioned problem, a memory access control apparatus is disclosed in Japanese Unexamined Patent Application, First Publication No. 2002-358232 (Patent Document 11). This memory access control apparatus performs memory access from both of a CPU as a first function device and a second function device to a memory, in which a memory address space is divided into a plurality of blocks so that each block has a continuous address region, and in which when the same memory block is accessed by the first and second function devices, the memory access control circuit allows simultaneous access by the first and second function devices to the memory if the accesses to the memory from both are for a read operation.
Furthermore, a multi-port DRAM is disclosed in Published Japanese Translation No. 2001-511559 of the PCT International Publication (Patent Document 12). This multi-port DRAM includes a multi-port internally-cached DRAM array, in which a plurality of system I/O resources are connected via common internal data buses connected to corresponding DRAM cores in each unit of the array, and in which, after one system I/O resource as a transmission source writes a message to the multi-port internally-cached DRAM array, this message is read and simultaneously transferred from the multi-port internally-cached DRAM array to all the system I/O resources that are required to receive this message.
However, the configuration described in the above Patent Document 11 has a problem in that it is not possible to simultaneously write the data which is input from one input/output port to each of the plurality of internal banks.
Furthermore, the configuration described in the above Patent Document 12 is for simply adapting a multi-cast to message interchange between the system I/O resources. This poses a problem in that, with a plurality of banks allocated to a plurality of MPUs or CPU cores, it is not possible to implement functions of a simultaneous write operation from one MPU or one CPU core to a plurality of banks, and conversely, a simultaneous read operation from one bank to a plurality of MPUs or CPU cores.